By Prof K M Bhurchandi, Prof A K Ray
ISBN-10: 1259006131
ISBN-13: 9781259006135
The 3rd version of this well known textual content keeps integrating easy recommendations, thought, layout and real-life purposes on the topic of the topic know-how, to permit holistic knowing of the ideas. The chapters are brought in music with the conceptual circulate of the topic with in-depth dialogue of options utilizing very good interfacing and programming examples in meeting language eatures: up-to-date with the most important issues like ARM structure, Serial communique normal USB New and up-to-date chapters explaining 8051 Microcontrollers, guideline set and Peripheral Interfacing besides Project(s) layout newest real-life purposes like difficult drives, CDs, DVDs, Blue Ray Drives
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Additional resources for Advanced Microprocessors and Peripherals 3e
Sample text
7. REDUNDANCY Memories require redundancy to ensure that sufficient chip yield is obtained. A redundant element is a piece of memory that can replace a defective piece of memory. Redundancy can come in the form of spare rows, VO,columns, blocks, or a combination of the above. Very small memories can get by without redundancy but large memories require significant numbers of redundant elements. When there are many small Static Random Access Memories 45 memories on a single chip, again some form of redundancy should be included or else yield will be negatively impacted.
Since reading a cell involves the cell pulling down either the true bit line or the complement bit line low, a resistive bit line contact causes one of the two data types to fail on these two cells. Thus, these two vertically paired cells with a defective bit line contact may be able to store and read either a "1" or a " 0 ' but not both. Furthermore, a resistive bit-line contact degrades the writing of the cells more than it degrades the reading of the cells. Because the SRAM cells in figures 2-7 and 2-8 are laid out differently, they fail differently as well.
For this illustration it is assumed that the chip is formed on a Pminus epitaxial layer and that no Pwell is required. Alternatively, the four NFETs at the bottom of the figure may be incorporated in a Pwell for a twin tub process. Figure 2-7. One layout for a six transistorSRAM cell. An alternative layout incorporates two ground contacts and two Vdd contacts. An example of this layout structure is shown in Figure 2-8. The area of a memory cell is the primary factor in the overall area of an embedded memory or a memory chip.
Advanced Microprocessors and Peripherals 3e by Prof K M Bhurchandi, Prof A K Ray
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