By Josyula R. Rao, Berk Sunar
ISBN-10: 3540284745
ISBN-13: 9783540284741
This e-book constitutes the refereed complaints of the seventh foreign Workshop on Cryptographic and Embedded platforms, CHES 2005, held in Edinburgh, united kingdom in August/September 2005.
The 32 revised complete papers offered have been rigorously reviewed and chosen from 108 submissions. The papers are prepared in topical sections on aspect channels, mathematics for cryptanalysis, low assets, exact goal undefined, assaults and countermeasures, mathematics for cryptography, relied on computing, and effective hardware.
Read Online or Download Cryptographic hardware and embedded systems-- CHES 2005: 7th international workshop, Edinburgh, UK, August 29-September 1, 2005: proceedings PDF
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Extra resources for Cryptographic hardware and embedded systems-- CHES 2005: 7th international workshop, Edinburgh, UK, August 29-September 1, 2005: proceedings
Example text
Instead of Step 6 the maximum likelihood principle uses Step 7. 1. Perform N1 + N2 measurements using a static key k and known data x1 , x2 , . .. 2. With regards to the attacked device select for each instant t the functions gi,t (·, ·) that span the vector subspace Fu;t . 3. Choose a selection function that combines kl and xl and apply Theorem 3 to a subset of N1 measurements to obtain the estimators h∗t (·, ·). ) 4. Choose instants t1 < · · · < tm . Use the complementary subset of N2 measurements to obtain the density f0 : IRm → IR.
Templates as Master Keys 19 Table 1. 35 our experiments, we chose the 50 highest peaks from this DPA metric to select significant points and built a pair of templates for these points for each s-box output bit using a single set of 1400 side channel samples. To estimate classification success rate, we classified the state of the 32 sbox output bits using a single set of another 100 random side channel samples measured from the same device. The classification success rates ηSi bj for the i-th s-box and j-th bit, 1 ≤ i ≤ 8 and 0 ≤ j ≤ 3, together with the corresponding entropy loss are shown in Table 1.
Multiple precomputed single-bit templates can lead to practical guided keyspace search algorithms using only a single sample from the target device. Moreover, single-bit attacks when combined with other attacks can result in much more devastating attacks as we show in the next section. 3 Attacking the Masking Countermeasure: Template-Enhanced DPA The proposed attack consists of two steps: a profiling phase and a hypothesis testing phase. In the profiling phase, the adversary, who is in possession of a test card with a biased RNG, builds templates, and in the hypothesis testing phase, the adversary uses these prebuilt templates to mount a DPA-like attack on a target card which is identical to the test card, but has a perfect RNG.
Cryptographic hardware and embedded systems-- CHES 2005: 7th international workshop, Edinburgh, UK, August 29-September 1, 2005: proceedings by Josyula R. Rao, Berk Sunar
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