By Bart Vermeulen, Kees Goossens (auth.)
This ebook describes an procedure and aiding infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), permitting its linked product to be brought into the industry extra quick. Readers examine step by step the major specifications for debugging a latest, silicon SOC implementation, 9 components that complicate this debugging activity, and a brand new debug procedure that addresses those necessities and complicating elements. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug technique is mentioned intimately, exhibiting the way it is helping to fulfill debug requisites and handle the 9, formerly pointed out components that complicate debugging silicon implementations of SOCs. The authors additionally derive the debug infrastructure requisites to help debugging of a silicon implementation of an SOC with their CSAR debug method. This debug infrastructure contains a widespread on-chip debug structure, a configurable computerized design-for-debug movement for use through the layout of an SOC, and customizable off-chip debugger software program. assurance contains an evaluate of the potency and effectiveness of the CSAR strategy and its helping infrastructure, utilizing six commercial SOCs and an illustrative, instance SOC version. The authors additionally quantify the fee and layout attempt to aid their approach.
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Additional resources for Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques
How do we combine the solutions to these related problems into one coherent debug approach and infrastructure? We limit the scope of these problems to the debugging of digital SOC implementation, because modern SOCs are predominantly digital . 13 shows a high-level overview of the proposed approach and the organization of this book. We perform an in-depth analysis on why debugging silicon implementations is difficult in Part II. We first perform this analysis for debugging a single building block in Chap.
Decide from which point in the execution of the SOC the observation should start, at which point it should stop, and at which intermediate points its internal signals are observed. Also choose an initial spatial scope for the reference, because observing the full spatial scope of the reference for the selected temporal scope may take a very long time, if this observability is obtained using a simulation environment. The temporal scope is the same for the silicon implementation and the reference.
Integration of Hardware Assertions in Systems-onChip. In Proc. IEEE International Test Conference, 2008. 11. Sandeep Kumar Goel and Bart Vermeulen. Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. Journal of Electronic Testing: Theory and Applications, 19(4):407–416, 2003. 12. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, and Steven Oostdijk. Test infrastructure design for the nexperia home platform pnx8550 system chip. In Proc. Design, Automation, and Test in Europe conference, 2004.
Debugging Systems-on-Chip: Communication-centric and Abstraction-based Techniques by Bart Vermeulen, Kees Goossens (auth.)