By Günter Böckle
ISBN-10: 354060054X
ISBN-13: 9783540600541
Many parallel computing device architectures are particularly suited to specific periods of purposes. even if, there are just a few parallel architectures both well matched for traditional courses. a lot attempt is invested into examine in compiler options to make programming parallel machines easier.
This publication provides equipment for computerized parallelization, in order that courses needn't to be adapted for particular architectures; right here the point of interest is on fine-grain parallelism, provided through so much new microprocessor architectures. The publication addresses compiler writers, desktop architects, and scholars through demonstrating the manifold advanced relationships among structure and compiler technology.
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Extra info for Exploitation of Fine-Grain Parallelism
Sample text
The scoreboard stalls instruction decoding if a decoded instruction will update a register for which this bit is already set, indicating a pending update; thus, write-after-write dependences are solved. Register renaming eliminates write-after-read and write-after-write dependences. When an instruction is decoded, its destination register is renamed by assigning a reorder-buffer location. A tag is used to identify the instruction's result; this tag is stored in the reorder-buffer location. When a subsequent instruction wants to read the renamed register, it gets the contents of the reorder-buffer location, either the computed value or the tag if the value is not computed yet.
Hardware has to provide fast busses to memory modules and register banks. The busses may be simple, in the TRACE machines they did not need arbitration logic because the scheduler determined bus usage statically at compile time. Thus, the busses could be made fast. 2. Memory Accesses For many machines and applications, memory access is a bottleneck, in VLIW and superscalar processors even more than in scalar processors because we have to feed several processing elements at a time with data from memory.
Dispensing bypasses would decrease performance significantly. g. the IBM VLIW which has an elaborate bypassing network. Many new ideas about methods for bypassing went into the design of the LIFE processor, the result of an operation flows into the "funnel files" of the processing units where this result will be needed later and such results wait in queues and will be accessed when they are needed. Again, such a solution will be expensive concerning hardware investment, space, and heat, when many processing elements are involved.
Exploitation of Fine-Grain Parallelism by Günter Böckle
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