Download PDF by Qing K. Zhu: High-Speed Clock Network Design

By Qing K. Zhu

ISBN-10: 1441953361

ISBN-13: 9781441953360

ISBN-10: 147573705X

ISBN-13: 9781475737059

High-Speed Clock community Design is a set of layout recommendations, innovations and learn works from the writer for clock distribution in microprocessors and high-performance chips. it really is geared up in eleven chapters.

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The key message is that for a device size x > x], the delay reduction is not significant but the power consumption increases because of the larger device sizes. We want to size down the "over-sized" devices in the circuit, while still satisfying the delay constraints, to reduce wasted power in the design. delay L - _ L -_ _ _ _ _ _ _ _-+ Transistor size Figure 3-13. Delay Trend Versus Device Sizes. 53 Chapter 3 Clocked Sequential Elements To further reduce power consumption, a sequential logic circuit having a series of latches for datapath logic may be modified as follows [125].

The latches are combined with the scan, reset, or set capabilities for more powerful functions and improving the testability in the design. The power consumption of the latch or flip-flop is a big concern in the highspeed design, because the clocking power takes a large portion of the entire chip power consumption. We describe two methods to reduce power consumption: (a) transistor sizing for the trade-off between the delay or speed and the transistor power or area; and (b) doing the clock gating based on the data valid flow.

RS-Type Latch Using NOR Gates [59]. Table 3-6. Truth Table for RS-Type Latch Shown in Figure 3-6 [59]. 2 RN 0 0 SN 0 0[0+1] 1 0 1 1 0 1 n.. 1 Q[n] ON[o+l] n.. 1 0 QN[n] Flip-Flop Clocking A flip-flop is consisted of two latches connected back to back, as shown in Figure 3-7. The fIrst latch is called the master latch and the second latch is called the slave latch. The clock of the slave latch is the inverted clock of the master latch. Therefore, if the master latch is open, the slave latch is closed, and vice versa.

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High-Speed Clock Network Design by Qing K. Zhu


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