By J. C. Cluley (auth.)
ISBN-10: 0333340612
ISBN-13: 9780333340615
ISBN-10: 1349064971
ISBN-13: 9781349064977
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Additional info for Interfacing to Microprocessors
Sample text
The following features are needed (a) An address register to drive the address lines, normally incremented after each byte has been transferred. (b) A byte counter register which is decremented after each transfer. (c) A zero-detecting gate attached to the byte counter register. This signals when the required number of bytes has been transferred, and is usually arranged to interrupt the processor. (d) Facilities for disabling the address and data line drivers in the processor, and holding up the processor during the transfer.
Only requests with a higher priority than this will be allowed to interrupt. 1 0, together with a status register and comparator. A further feature is that the 8214 can be cascaded by attaching the output of another 8214 to each input, so providing 64 priority inputs. When the Intel 8085 was designed some time later, a more complex interrupt package was introduced, which is also compatible with 8080 systems. This is the 8259 Programmable Interrupt Controller. It performs in a similar manner to the 8214 in having eight inputs and a register holding the status of the current routine, but it gives greater flexibility in that the move to the service routine is made by a 'CALL' or 'JUMP TO SUBROUTINE' instruction.
VMA, if the VMA signal has not been gated in elsewhere. VMA signifies that the information on the address lines is a valid address which may be decoded. At certain times in the processor cycle the address lines indicate the contents of the index register or the stack pointer. VMA is low at these times, so ensuring that these register contents are not interpreted as addresses. Reset is connected to the Reset pin of the CPU and is held low for a few Input/Output Packages 25 milliseconds when power is applied to the system, so clearing the six registers in the PIA.
Interfacing to Microprocessors by J. C. Cluley (auth.)
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