By Prabhat Mishra
ISBN-10: 0080558372
ISBN-13: 9780080558370
ISBN-10: 0123742870
ISBN-13: 9780123742872
Effective layout of embedded processors performs a severe position in embedded structures layout. Processor description languages and their linked specification, exploration and quick prototyping methodologies are used to discover the absolute best layout for a given set of purposes below a variety of layout constraints, reminiscent of region, strength and function. This booklet is the 1st, entire survey of contemporary structure description languages and should be a useful reference for embedded procedure architects, designers, builders, and validation engineers. Readers will see that using specific structure description languages will result in productiveness profits in designing specific (application-specific) different types of embedded processors. * finished assurance of all smooth structure description languages... use the fitting ADL to layout your processor to suit your application;* most recent details to be had approximately every one structure description language from the developers...save time chasing down trustworthy documentation;* Describes how every one structure desccription language permits key layout automation initiatives, akin to simulation, synthesis and testing...fit the ADL for your layout cycle;
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Extra info for Processor Description Languages, Volume 1
Example text
Simulation is the most widely used form 27 28 CHAPTER 2 ADL-driven Methodologies of processor validation. Use of ADL specification improves the overall validation effort, since both simulator and directed tests can be automatically generated from the ADL specification, as shown in Fig. 6. The generated tests can be applied on the hardware implementation as well as on the generated cycle-accurate simulator (reference model), and the outputs can be compared to check the correctness of the implementation.
It is also necessary to ensure that execution of each operation is completed in a finite amount of time. Similarly, it is important to verify the execution style of the architecture. Typical validation scenario requires two models: specification (assumed to be correct) and implementation (needs to be verified). A set of tests can be applied on both specification (or its simulatable model) and implementation, and the corresponding outputs can be compared. However, in case of specification validation, we have only one model that needs to be verified.
9 Concerning processor architectures, the most recent trend is the introduction of RISC processors by John Hennessy [23] and others. Dataflow computers emerge as a new and initially promising direction [24]. VLIW processors are hardly considered. There is Baba's microcode compiler [25]. The thesis of Cattell [26] provides insights into the generation of code generators. Glanville and Graham propose a table-driven code generator [27]. A survey by Ganapathi et al. summarizes the state of the art in retargetable compilation [28].
Processor Description Languages, Volume 1 by Prabhat Mishra
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