By Kerry Bernstein
ISBN-10: 0306470136
ISBN-13: 9780306470134
ISBN-10: 0387740996
ISBN-13: 9780387740997
ISBN-10: 0792377621
ISBN-13: 9780792377627
Industry call for for microprocessor functionality has inspired persevered scaling of CMOS via a succession of lithography generations. Quantum mechanical obstacles to persisted scaling are turning into simply obvious. in part Depleted Silicon-on-Insulator (PD-SOI) know-how is rising as a promising technique of addressing those obstacles. It additionally introduces extra layout complexity which has to be good understood. SOI Circuit layout ideas first introduces the coed or working towards engineer to SOI machine physics and its primary idiosyncrasies. It then walks the reader via realizations of those mechanisms that are saw in universal high-speed microprocessor designs. ideas of thumb and comparisons to standard bulk CMOS are provided to lead implementation. SOI's final virtue, although, may well lie within the detailed circuit topologies it helps; a few those novel new techniques is additionally defined. SOI Circuit layout strategies attracts upon the most recent undefined literature in addition to the firsthand reports of its authors. it really is an excellent creation to the suggestions of governing SOI use and presents an organization origin for extra research of this interesting new know-how paradigm.
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Additional info for SOI Circuit Design Concepts
Example text
Substrate Bias Effect and Source-Drain Breakdown Characteristics on Body-Tied Short-Channel SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 46, No. 1, January 1999, pp. 151 -158. 6] D. , “Generation-Recombination Transient Effects in Partially Depleted SOI Transistors: Systematic Experiments and Simulations,” IEEE Trans. Electron Devices, Vol. 45, No. 8, Aug. 1998, pp. 1678-1683. 7] A. J. 3-10. 1 Introduction So many currents in such a little puddle! 1 As described in the previous chapter, the SOI device is essentially identical to the bulk MOSFET well known to the industry, with the addition of an insulating layer under a thin active silicon region.
This technique allows for the gate voltage to be maintained such that it does not effect the diodes current carrying capabilities. One should note that if the diode is used for an electro-static discharge protect device, (ESD Diode), on a multivoltage chip, the voltage of the output driver may cause the gate of the diode to exceed the reliability tolerance of the thin oxide. In this case, the gate should be driven to an intermediate voltage level that maintains the reliability of the oxide. One complication of the poly bounded diode on SOI is that the series resistance is larger.
This wafer is now the substrate for the SOI wafer. A thermal anneal creates a stress fracture along the plane of the hydrogen implant. This is the Smart Cut. The original silicon wafer can be removed from the trilayer stack leaving behind a thin layer of silicon on the top of the buried oxide. The removed portion of the silicon wafer will become the substrate for another smart cut wafer. In this manner, no silicon is wasted. To finish process, the SOI wafer is annealed and polished to prepare the surface for traditional CMOS processing steps.
SOI Circuit Design Concepts by Kerry Bernstein
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