By Etienne Andre, Romain Soulat(auth.)
ISBN-10: 1118569350
ISBN-13: 9781118569351
ISBN-10: 1848214472
ISBN-13: 9781848214477
This publication introduces state of the art verification recommendations for real-time embedded platforms, in keeping with the inverse strategy for parametric timed automata. It experiences well known formalisms for the specification and verification of timed concurrent structures and, particularly, timed automata in addition to a number of extensions reminiscent of timed automata built with stopwatches, linear hybrid automata and affine hybrid automata.
The inverse technique is brought, and its merits for making certain robustness in real-time structures are proven. Then, it really is proven how an new release of the inverse technique can clear up the great parameters challenge for parametric timed automata via computing a behavioral cartography of the approach. diverse extensions are proposed rather for hybrid platforms and purposes to scheduling difficulties utilizing timed automata with stopwatches. numerous examples, either from the literature and undefined, illustrate the thoughts in the course of the book.
Various parametric verifications are played, particularly of abstractions of a reminiscence circuit offered by means of the chipset producer ST-Microelectronics, in addition to of the possible flight keep an eye on procedure of the subsequent new release of spacecraft designed by way of ASTRIUM area Transportation.
Contents:
1. Parametric Timed Automata.
2. The Inverse procedure for Parametric Timed Automata.
3. The Inverse procedure in perform: program to Case Studies.
4. Behavioral Cartography of Timed Automata.
5. Parameter Synthesis for Hybrid Automata.
6. program to the Robustness research of Scheduling Problems.
7. end and Perspectives.
Content:
Chapter 1 Parametric Timed Automata (pages 1–22): Etienne Andre and Romain Soulat
Chapter 2 The Inverse technique for Parametric Timed Automata (pages 23–54): Etienne Andre and Romain Soulat
Chapter three The Inverse process in perform: software to Case experiences (pages 55–80): Etienne Andre and Romain Soulat
Chapter four Behavioral Cartography of Timed Automata (pages 81–102): Etienne Andre and Romain Soulat
Chapter five Parameter Synthesis for Hybrid Automata (pages 103–120): Etienne Andre and Romain Soulat
Chapter 6 program to the Robustness research of Scheduling difficulties (pages 121–132): Etienne Andre and Romain Soulat
Chapter 7 end and views (pages 133–136): Etienne Andre and Romain Soulat
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Additional info for The Inverse Method
Example text
The semantics of parametric timed automata is given in the following under the form of a labeled transition system. – Let A = (Σ, Q, q0 , X, P, K, I, →) be a parametric timed automaton. The symbolic semantics of A is the labeled transition system (S, S0 , ⇒) over Σ where S = {(q, C) ∈ Q × L(X ∪ P ) | C ⊆ I(q)}, ∧H−1 S0 = {(q0 , K ∧ I(q0 ) ∧ i=1 xi = xi+1 )} 16 The Inverse Method a a d and a transition (q, C) ⇒ (q ′ , C ′ ) belongs to ⇒ if ∃C ′′ : (q, C) → (q ′ , C ′′ ) → (q ′ , C ′ ), with: a • discrete transitions (q, C) → (q ′ , C ′ ) if there exists (q, g, a, ρ, q ′ ) ∈ → and (( ) ) C ′ = C(X) ∧ g(X) ∧ X ′ = ρ(X) ↓X ′ ∪P ∧ I(q ′ )(X ′ ) , and ′ [X ←X] d • delay transitions (q, C) → (q, C ′ ) with C ′ = C↑ ∧ I(q)(X).
We have ∩ S = Post ∗A(K) ({s0 }) and K0 = (q,C)∈S C↓P . – We have K0 ⊆ K. P ROOF. 2, for ∩ all states (q, C) ∈ S, we have C↓P ⊆ K, since S = Post ∗A(K) ({s0 }). As K0 = (q,C)∈S C↓P , then K0 ⊆ K. – We have π0 |= K0 . P ROOF. e. π0 |= C↓P , for all (q, C) ∈ S). ∩ Thus, the intersection K0 of the constraints associated with the states of S, that is (q,C)∈S C↓P , is satisfied by π0 . Let us now show that the set of traces in the concrete semantics and the set of traces in the symbolic semantics are equal.
The initial location q0 corresponds to the initial levels of the signals according to the environment. 1(b) on page xv. Therefore, we have the implicit constraint TSetup ≤ TLO ∧ THold ≤ THI . 1. Parametric timed automaton modeling a “NOT” gate We consider that the circuit has a good behavior if it verifies the following property Prop 1 : “every trace contains both Q↗ and CK ↘ , and Q↗ occurs before CK ↘ ”. That is, the raise of signal Q must occur before the fall of signal CK . ) Let us study the behavior of the flip-flop circuit under π0 .
The Inverse Method by Etienne Andre, Romain Soulat(auth.)
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