By Rainer Leupers
The construction blocks of modern and destiny embedded platforms are advanced highbrow estate elements, or cores, a lot of that are programmable processors. regularly, those embedded processors ordinarily were professional grammed in meeting languages as a result of potency purposes. this suggests time eating programming, huge debugging, and coffee code portability. the necessities of brief time-to-market and dependability of embedded platforms are patently far better met by utilizing high-level language (e.g. C) compil ers rather than meeting. although, using C compilers usually incurs a code caliber overhead in comparison to manually written meeting courses. a result of desire for effective embedded structures, this overhead needs to be very low so as to make compilers precious in perform. In flip, this calls for new compiler strategies that take the categorical constraints in embedded process de signal into consideration. An instance are the really expert architectures of contemporary DSP and multimedia processors, which aren't but sufficiently exploited via present compilers.
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Extra info for Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
17. Addressing with seven ARs algorithm for optimized array index allocation. This technique will be presented in more detail in the next section. A different approach has been taken in [Gebo97a], where also physical AR limits have been incorporated into array index allocation. However, both techniques do not explicitly consider the address modifications required at the end of loop iterations. 3 OPTIMAL AR ALLOCATION IN LOOPS PROBLEM FORMULATION Consider a loop with a sequence of accesses (a 1 , ...
In [LeMa95a], a related scheduling technique based on Integer Linear Programming has been presented, capable of exactly meeting time constraints for DSP algorithms. This technique has also been applied to optimized code selection and scheduling in presence of strongly encoded instruction formats [LeMa96a]. Several important contributions to code generation for embedded processors came from the SPAM project. These include an adaptation of the tree parsing technique for code selection to irregular architectures [ArMa95], minimization of mode switching instructions in DSPs [LD K+95a], and partitioning of program variables among multiple memory banks [SuMa95].
Note that the above formulation captures only a simple special case: offset assignment for one AR and zero MRs. We will later generalize this formulation towards more relevant sets of AGU parameters. 2 RELATED WORK The first offset assignment algorithm was presented by Bartley [Bart92]. We will use the notation ( k, m, r) -OA to denote concrete AGU parameter configurations. Bartley considered (1,0,1)-0A and modeled the problem by means of an undirected edge-weighted access graph G = (V, E, w), where Vis the set of variables, and for each edge e = (vi, v2 ) E E, the weight w (e) is equal to the number of transitions (vi, v 2 ) or (v 2 , vi) in the access sequence S.
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools by Rainer Leupers