By Hideo Fujiwara
ISBN-10: 0262060965
ISBN-13: 9780262060967
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Additional info for Logic testing and design for testability
Example text
On the other hand, in PODEM, the initial objective (0, L) is determined to set up the faulty signal D to L, and backtrace starts. 24(b), the back trace causes a path from L backward to a primary input B. The assignment B = implies L = 1 and fails to provide the faulty signal on L. As seen in this example, by assigning uniquely determined values we can avoid the unnecessary choice . 25(a). Supposing that the D-frontier consists of a single gate, we often have specific paths such that every path from the site of the D-frontier to a primary output always goes through those paths.
However, X 2 = X 3 = 1 and X 4 = 0 implies G7 = 0, which is an inconsistency. 7 Multiple-path sensitizatio n pa th G. G, must also fail. This incon sisten cy seems to imply th at the fau lt cannot be detected. However, th e input pattern x, = X , = x, = x. = 1 provides a test for the fault in qu estion. 7 shows the behavior of bot h normal and fault y circu its for this inp ut. In this figure, we notice that the effect of the fault has been propagate d simultaneou sly along two paths. The single-path sensitizat ion method failed to derive the test because it allowed only one path to be sensitized at a time.
The test pattern th at detects the fault ex is an input combination or vector X th at satisfies F(X) EEl F,(X) = 1. Us ing some arithmetic. 1 = xjFi(O) EB xjFi(O) EB XiFi(l) EB x;Fj(O) = x j ( Fj (1 ) EB Fi(O)) dF(X) - ยท dXi =X i - Thus the set of all tests that detect the fault = { x. x. dF(X) dx, , I Xi s-a-O is l} and is defined by the Boolean expression This expression implies that Xi = land dF[dx, = 1. Since Xi = 1, then Xi applies the opposite value on the faulty input. The factor dF/dx j ensures that this erroneous signal affects the value of F.
Logic testing and design for testability by Hideo Fujiwara
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