By MindShare Inc., Tom Shanley
ISBN-10: 0201309734
ISBN-13: 9780201309737
This sequence of books is really a huge a part of my library...I might suggest them to somebody doing layout or aid, in addition to to any builders who write low-level approach code. -Paula Tomlinson, home windows Developer's magazine Pentiumi professional and Pentiumi II procedure structure, moment variation, information the interior structure of those processors, describing their and software program features, the bus protocol they use to speak with the method, and the general desktop structure. It additionally describes the BIOS replace function. Written for desktop and software program engineers, this booklet deals perception into how the Pentium seasoned and Pentium II family members of processors interprets legacy x86 code into RISC directions, executes them out-of-order, after which reassembles the outcome to check the unique software move. In detailing the Pentium seasoned and Pentium II processors' inner operations, the booklet unearths why the processors generate quite a few transaction forms and the way they computer screen bus site visitors generated via different entities to make sure cache consistency. This new version contains accomplished insurance of the Pentium II processor.It highlights the variations among the Pentium seasoned and Pentium II processors, specifically, the Slot 1 connector and the processor cartridge layout used by the Pentium II and meant to be used in destiny Intel processors. It positive aspects the Pentium II's aid for the MMX guide set and registers, and exhibits the way it is optimized for 16-bit code execution. This publication additionally describes the Pentium II's L2 cache and its aid for power-conservation modes.Pentiumi professional and Pentiumi II process structure, moment version, additionally covers: *the courting of Pentium seasoned and Pentium II processors to different processors, PCI bridges, caches, and reminiscence *detailed descriptions of the information, code, and L2 caches *power-on configuration and processor startup *transaction deferral *instruction, check in set, paging, and interrupt improvements to the Pentium seasoned and Pentium II *BIOS replace characteristic *Machine fee structure *performance tracking and the Time Stamp Counter *MMX check in and guide set supported through the Pentium II *overview of the Intel 450KX, 450GX, and 440FX chipsets the computer approach structure sequence is a crisply written and entire set of publications to an important computer criteria. every one identify is designed to demonstrate the connection among the software program and and explains completely the structure, gains, and operations of structures equipped utilizing one specific form of chip or specification. 0201309734B04062001
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Extra info for Pentium Pro and Pentium II System Architecture (2nd Edition)
Sample text
142 Basic Relationship of the MTRRs to Paging.......................................................... 143 Type if Paging and MTRRs enabled and Address Covered by Both ................ 144 Results of External Snoop Presented to Code Cache........................................... 159 Results of External Snoop Presented to Data Cache............................................ 178 Results of External Snoop Presented to L2 Cache................................................ 188 Toggle Mode Quadword Transfer Order..............................................................
43 Bit Assignment of EBL_CR_POWERON MSR ....................................................... 45 Effects of Reset on CPU.............................................................................................. 52 Pipeline Stages............................................................................................................. 82 Decoder Throughput Table ....................................................................................... 86 Basic Composition of a ROB Entry.........................................................................
This information is then stored in non-volatile memory in the form of a table (the MP, or multiprocessing, table). An MP (Multi-Processing) OS uses this information to determine the available processors, their types and features. , DOS) only makes use of the BSP. The other processors remain dormant (in other words, they’re useless). book Page 14 Friday, September 8, 2000 6:30 AM Pentium Pro and Pentium II System Architecture Assuming that it is an MP OS, it assigns a task to a processor in the following manner: • • • Typically, it instructs a bus mastering disk controller to load a task into memory.
Pentium Pro and Pentium II System Architecture (2nd Edition) by MindShare Inc., Tom Shanley
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