By Stuart Sutherland
ISBN-10: 1461356911
ISBN-13: 9781461356912
ISBN-10: 1461517133
ISBN-13: 9781461517139
by Phil Moorby The Verilog Description Language has had an awesome impression at the mod em electronics undefined, considering the fact that the fundamental composition of the language used to be built in a shockingly brief time period, early in 1984. given that its introduc tion, Verilog has replaced little or no. through the years, clients have asked many increase ments to satisfy new technique wishes. yet, it's a advanced and time eating procedure so as to add positive aspects to a language with no ambiguity, and protecting consistency. a gaggle of Verilog fanatics, the IEEE 1364 Verilog committee, have damaged the Verilog function doldrums. those contributors could be applauded. They invested the time and effort, frequently their own time, to appreciate and get to the bottom of an intensive wish-list of language improvements. They took at the job of selecting a characteristic set that might withstand the scrutiny of the standardization procedure. i want to consistent with sonally thank this workforce. they've got proven that it truly is attainable to conform Verilog, instead of having to fully begin over with a few innovative new language. The Verilog 1364-2001 commonplace presents a number of the complicated construction blocks that clients have asked. The improvements comprise key parts for verification, summary layout, and different new technique functions. As designers take on complicated matters corresponding to automatic verification, method partitioning, etc., the Verilog general will upward push to fulfill the ongoing problem of electronics design.
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Additional info for Verilog — 2001: A Guide to the New Features of the Verilog® Hardware Description Language
Example text
Most net declarations can be inferred rather than explicitly declared. However, the inference of net data types can also introduce bugs in a design that may be difficult to find. In the following example, there are three problems in the module, due to mis-typed signal names. With Verilog-1995, these invalid signal names will automatically infer nets, and so the module will compile, even though there are errors. module bad_chip (01, nO, nl); output 01; input nO, nl; wire wire 01; nO, nl; and (01, nO, nl); Ilthere are 3 typos in this linel endmodule S.
To behave like combinational logic, the addition and multiplication statements should be evaluated whenever any of the inputs change. In the preceding example, however, c might change dozens of times, and the product will not be re-evaluated. This last example is not using the @* token in the way with which it is intended. While syntactically allowable, it does not model the behavior of combinational logic. It is only when the @* or @( *) tokens are placed at the very beginning of a procedure, before the single statement or begin-end block in the procedure that these tokens represent combinational logic sensitivity.
54 Verilog-2001: A Guide to the New Features of the Verilog HDL 24. Power operator Background Verilog-1995 provides addition, multiplication and shift-left operators. While these operators can be used to raise one number to the power of another, they require using procedural programming statements, such as a for loop. As an example, one of the ways to calculate the value of mn in Verilog-1995 is to do repeated multiplication operations in a loop, as in the following function: function [63:0) pow; input m, n; integer m, n; begin i f (n < 0) pow = 64'bx; else if (n == 0) pow 1; else for (pow = 1; n > 0; n pow = pow * m; end n - 1) An example of using the preceding function is: always @(posedge clock) result = pow (base, exponent); What's new V eriIOg-2001 adds a power operator, **, to the Verilog language.
Verilog — 2001: A Guide to the New Features of the Verilog® Hardware Description Language by Stuart Sutherland
by Daniel
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