By Ulrich Golze
ISBN-10: 3642610013
ISBN-13: 9783642610011
ISBN-10: 3642646506
ISBN-13: 9783642646508
This publication introduces to fashionable layout of enormous chips. a robust RISC processor within the variety of a SPARC is apecified in a description language (HDL), it's built hierarchically and is eventually despatched as a gate version to the silicon seller LSI good judgment for construction. The ensuing processor on a semi-custom gate-array chip with greater than 50.000 used gates and an potency of as much as forty MIPS is validated on an automated attempt gear and a testboard. The e-book additionally introduces completely to the HDL VERILOG. The integrated disk comprises greater than forty small and medium sized executable VERILOG examples, the massive processor types and the VERILOG simulator VeriWell working on computing device or SPARC.
Read or Download VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design PDF
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Additional info for VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design
Example text
While in the general case, ATE test patterns have to be developed again at the gate level in a time-consuming manner, it suffices in our case of a RISC processor to extract ATE patterns from the existing functional test programs and to extend them by some additional patterns. A number of tester-specific restrictions have to be observed. 3 The Design Phases 21 Moreover, the production test patterns are expected to have a high fault coverage. By this, we mean the percentage of faults discovered with respect to all faults of a fault model.
The input format approximates known formats of other processors. Oriented to RISe typical aspects, it has a 3-operand scheme: operation destination register, source register1, source register2 or operation destination register, source register1, constant . A configurable code generation is meaningful, as it may change. Not only the bit pattern but also syntactical rules should be easily modifiable. 1 The RISe Processor at Work 49 processor is not a bottleneck and does not produce many costs. The reason lies in the simply structured RISC-typical instruction set.
This includes the meanings and results of all instructions (semantics). The programmer is informed about the interrupt mechanism and useful features for operating systems. In addition, there are implications of the planned architecture, such as a delay slot, processor mode, and the memory concept. The internal specification describes the processor from the view of a designer and sketches a coarse design path. This includes requirements for the internal structure like caches, the implementation of the instruction set on a datapath, and the organization as a pipeline structure, as well as a description of processor control.
VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design by Ulrich Golze
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