By Nasser Kehtarnavaz
ISBN-10: 1598290525
ISBN-13: 9781598290523
ISBN-10: 1598290533
ISBN-13: 9781598290530
This ebook offers an outline of the information and methods for transitioning a picture or video processing set of rules from a examine atmosphere right into a real-time limited surroundings. Such guidance and techniques are scattered within the literature of assorted disciplines together with photo processing, machine engineering, and software program engineering, and therefore haven't formerly seemed in a single position. through bringing those techniques into one position, the ebook is meant to serve the larger group of researchers, training engineers, commercial execs, who're attracted to taking a picture or video processing set of rules from a study setting to an exact real-time implementation on a source limited platform. those ideas include set of rules simplifications, architectures, and software program equipment. in the course of the ebook, conscientiously chosen consultant examples from the literature are awarded to demonstrate the mentioned strategies. After analyzing the e-book, the readers are uncovered to a large choice of ideas and instruments, which they could then hire to layout a real-time photograph or video processing approach.
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Extra info for Real-time image and video processing: from research to reality
Example text
Since pixel data are usually represented by 8-bits or 16-bits, and since most modern processors have 32-bit registers, packed data processing allows packing four 8-bit pixels or two 16-bit pixels into 32-bit registers and then issuing an instruction to be performed on the individual 8-bit or 16-bit pixels at the same time. These types of packed data instructions not only alleviate the computation burden of low-level and intermediate-level operations, but also help to reduce memory access bottlenecks because multiple pixel data can be read using one instruction.
Current generation FPGAs can be either fully reconfigured or partially reconfigured, with reconfiguration times of less than 1 ms, making it possible to have a dynamic run-time reconfiguration. This configuration is useful for reducing system size of embedded devices. The interested reader can refer to [2, 14, 22, 83, 140] for more information on run-time reconfigurations of FPGAs for image/video processing applications. Due to their programmable nature, FPGAs can be programmed to exploit different types of parallelism inherent in an image/video processing algorithm.
In [51, 118, 119], it was shown that by using the DSP platform, a real-time video rate edge-preserving, nonlinear filtering could be achieved for Quarter Common Image Format (QCIF) sized video sequences. In [120], the extension of the nonlinear filtering algorithms to 3D was demonstrated using a single-chip DSP platform. 2 Computationally Complex Operations Another computationally complex algorithm for which a single-chip, high-performance DSP has been utilized is automatic color reduction in the CbCr chrominance color space using the two-dimensional (2D) version of a multiscale clustering algorithm [107].
Real-time image and video processing: from research to reality by Nasser Kehtarnavaz
by David
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